Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Functional processor-based testing of communication peripherals in systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Functional Verification Coverage Measurement and Analysis
Functional Verification Coverage Measurement and Analysis
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Practical Design Verification
CPU Testability in Embedded Systems
DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Microprocessor Software-Based Self-Testing
IEEE Design & Test
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Today's SoCs are composed of a wide variety of modules, such as microprocessor cores, memories, peripherals, and customized blocks directly related to the targeted application. To effectively perform simulation-based design verification of peripheral cores, it is necessary to stimulate the description in a broad range of behavior possibilities, checking the produced results. Different strategies for generating suitable stimuli have been proposed by the research community to functionally verify these modules and their interconnection when embedded in a SoC: however, their verification often remains a largely manual and unstructured operation. In this paper we describe a general approach to develop concise and effective sets of inputs by modeling the configuration modes of a peripheral with a graph, and creating paths able to cover all of its nodes: proper stimuli for the device are then directly derived from the paths. The resulting inputs sequences are aimed at design verification of system peripherals such as DMA controllers, and can be applied via simulation by means of dedicated testbenches or by setting up an environment including a processor, which executes a proper test priogram. In the latter case, the developed programs can be exploited in later stages for testing, by adding suitable observability features. Experimental results demonstrating the method effectiveness are reported.