An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores

Authors:
L. Bolzani;E. Sanchez;M. Schillaci;M. Sonza Reorda;G. Squillero
Affiliations:
Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy;Politecnico di Torino, Italy
Venue:
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Year:
2007

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Abstract

Test of peripheral modules has not yet been deeply investigated by the research community. When embedded in a system on a chip, peripheral cores introduce new issues for post-production testing. A peripheral core embedded in a SoC requires a test set able to properly perform two different tasks: configure the device in different operation modes and properly exercise it. In this paper an automatic approach able to generate test sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The method compares favorably with results obtained by hand.