Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Fault-tolerant computer system design
Fault-tolerant computer system design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
An RT-level fault model with high gate level correlation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Native Mode Functional Self-Test Generation for Systems-on-Chip
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
Integrating BIST Techniques for On-Line SoC Testing
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Efficient techniques for automatic verification-oriented test set optimization
International Journal of Parallel Programming
A software test program generator for verifying system-on-chips
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Test Generation for Microprocessors
IEEE Transactions on Computers
An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
| Hi-index | 0.00 |
Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardware techniques for testing processors embedded in SoCs. However, the test of the surrounding peripherals has not been the subject of many research works, even if their importance within the entire system may be considerable. In this paper we focus on Software-based Self-Test techniques for testing peripheral components within a SoC and explore the possibility that test generation only relies on high-level metrics. We outline a possible test generation and application flow, and discuss the suitability of different RT-level metrics. By exploiting a sample case study, we quantitatively evaluate the effectiveness of the different metrics and the practical viability of the considered approach. As a major contribution, the paper shows that for peripheral components the relationship between high-level and gate-level metrics is higher than for the general case.