ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
Logic-level analysis of high-level faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Proceedings of the 20th annual conference on Integrated circuits and systems design
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
An evolutionary methodology for test generation for peripheral cores via dynamic FSM extraction
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
| Hi-index | 0.00 |
With the advent of new RT-level design and test flows, new tools are needed to migrate at the RT-level the activities of fault simulation testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of VHDL simulators to compute faulty responses. The simulator was implemented as a phototypical tool, and experimental results show that simulation of a faulty circuit is no more costly than simulation of the original circuit. The reliability of the fault coverage figures computed at the RT-level is increased thanks to an analysis of inherent VHDL redundancies, and by foreseeing classical synthesis optimizations. A set of "rules" is used to compute a fault list that exhibits good correlation with stuck-at faults.