IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Art of Software Testing
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level
Proceedings of the IEEE International Test Conference 2001
AMLETO: a multi-language environment for functional test generation
Proceedings of the IEEE International Test Conference 2001
B-algorithm: A Behavioral-Test Generation Algorithm
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
An RT-level fault model with high gate level correlation
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Logic-level analysis of high-level faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Functional Fault Coverage: The Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage?
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
High-level and hierarchical test sequence generation
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
OCCOM-efficient computation of observability-based code coverage metrics for functional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault-diagnosis-based technique for establishing RTL and gate-level correspondences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An EFSM-based approach for functional ATPG
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
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Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available.On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model?The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology.