Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
| Hi-index | 0.00 |
More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.