AMLETO: a multi-language environment for functional test generation

An error simulation based approach to measure error coverage of formal properties

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Protected IP-core test generation

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Mixing ATPG and property checking for testing HW/SW interfaces

Proceedings of the 13th ACM Great Lakes symposium on VLSI

References

SystemC

Logic-level analysis of high-level faults

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Laerte++: an object oriented high-level TPG for systemC designs

Languages for system specification

Logic-level mapping of high-level faults

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Redundant functional faults reduction by saboteurs synthesis [logic verification]

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Priority directed test generation for functional verification using neural networks

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

A framework for the functional verification of systemC models

International Journal of Parallel Programming

Properties Incompleteness Evaluation by Functional Verification

IEEE Transactions on Computers

Simulated fault injections and their acceleration in SystemC

Microprocessors & Microsystems

Logic-level mapping of high-level faults

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation

Microprocessors & Microsystems