The case for design using the World Wide Web
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Computer networks: a systems approach
Computer networks: a systems approach
Java as a specification language for hardware-software systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Data security for Web-based CAD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Specification and validation of disstributed IP-based designs with JavaCAD
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Verification and management of a multimillion-gate embedded core design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Web-CAD methodology for IP-core analysis and simulation
Proceedings of the 37th Annual Design Automation Conference
Virtual fault simulation of distributed IP-based designs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional test generation for behaviorally sequential models
Proceedings of the conference on Design, automation and test in Europe
AMLETO: a multi-language environment for functional test generation
Proceedings of the IEEE International Test Conference 2001
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Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. IPs are usually provided with their own test patterns that can be used only by applying design for testability techniques onto the chip. Whenever physical faults must be detected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test generationon faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. Finally, remote simulation can be also performed locally to avoid bandwidth bottleneck and the test generation process can be indifferently applied at lower abstraction levels such as RT and gate.