Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic functional vector generation for VHDL specifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level
Proceedings of the IEEE International Test Conference 2001
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
AMLETO: a multi-language environment for functional test generation
Proceedings of the IEEE International Test Conference 2001
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-level and hierarchical test sequence generation
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Logic-level analysis of high-level faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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High-level descriptions of digital systems are perturbed by using high-level fault models in order to perform functional verification. Fault lists should be accurately created in order to avoid waste of time during ATPG and fault simulation. However, automatic fault injection tools can insert redundant faults which are not symptoms of design errors. Such redundant faults should be removed from the fault list before starting the verification session. This paper proposes an automatic strategy for high-level faults injection, which removes redundant bit coverage faults. An efficient implementation of a bit coverage saboteur is proposed, which allows one to use synthesis for redundant faults removal. Experimental results highlight the effectiveness of the methodology. By using the proposed injection strategy, functional APTG time is reduced and fault coverage is increased.