Logic-level analysis of high-level faults
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Functional Verification of Networked Embedded Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
High-level test generation for hardware testing and software validation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Logic-level mapping of high-level faults
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
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Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.