Formal verification meets simulation (embedded tutorial) (abstract only)
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MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
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ICFEM '98 Proceedings of the Second IEEE International Conference on Formal Engineering Methods
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HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
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Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
System/network design-space exploration based on TLM for networked embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper we propose an automatic mechanism to extract the environment of a networked embedded system (NEV), and a functional verification methodology, which mixes automatic test pattern generation and model checking, exploiting the network environment constraints.