Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Exploiting Behavioral Information in Gate-Level ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic execution and program testing
Communications of the ACM
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Practical System for Mutation Testing: Help for the Common Programmer
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
High-Level Observability for Effective High-Level ATPG
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
High-level and hierarchical test sequence generation
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Reliability of the Path Analysis Testing Strategy
IEEE Transactions on Software Engineering
Automatic Generation of Validation Stimuli for Application-Specific Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Project verification and construction of superchip tests at the RTL level
Automation and Remote Control
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It is now common for design teams to develop systems where hardware and software components cooperate; they are thus facing the challenging task of validating and testing systems where hardware and software parts exist. In this paper a high-level test generation approach is presented, which is able to produce input stimuli that can be fruitfully exploited for test and validation purposes of both hardware and software components. Experimental results are reported showing that the proposed approach produces high quality vectors in terms of the adopted metrics for hardware and software faults.