Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
High-level synthesis for easy testability
EDTC '95 Proceedings of the 1995 European conference on Design and Test
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RT-level TPG Exploiting High-Level Synthesis Information
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-level test generation for hardware testing and software validation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
| Hi-index | 0.01 |
This paper aims at broadening the scope of hierarchicalATPG to the behavioral-level. The main problem is identified, namelythe mismatch of timing models between the behavioral- andgate-levels. As a main contribution of this paper, a theoreticalanalysis of this problem led to the definition of a novel concept,that of dominated patterns, that captures the needed linkbetween the levels. Some metrics are defined, taken from the softwarerealm, that allow generation of test patterns at thebehavioral-level. To validate the concept correctness, different ATPGsystems are presented, and experimental results show an improvementin the test quality, thanks to the exploitation of behavioral-levelinformation.