Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
The modeling and synthesis of bus systems
DAC '81 Proceedings of the 18th Design Automation Conference
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Exploiting Behavioral Information in Gate-Level ATPG
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
| Hi-index | 0.00 |
This paper presents an attempt towards design quality improvement by incorporation of testability features during datapath high-level synthesis. This method is based on the use of hardware sharing possibilities to improve the testability of the circuit without a time consuming re-synthesis process. This is achieved by incorporating test constraints during register allocation and interconnect network generation. The main features of this method are: a test analysis at the behavioral level rather than at a structural one; the non limitation on the behavioral descriptions (loops, control constructs are supported); and the optimized test area overhead and CPU time compared to standard approach. The method was applied to several benchmarks resulting in easily testable designs for almost the same area costs as the original (without testability) designs.