Analyzing Testability from Behavioral to RT Level

Authors:
M. L. Flottes;R. Pires;B. Rouzeyre
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier 2, UMR CNRS 5506, 161 rue Ada, 34392 Montpellier Cedex 5, FRANCE;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier 2, UMR CNRS 5506, 161 rue Ada, 34392 Montpellier Cedex 5, FRANCE;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier 2, UMR CNRS 5506, 161 rue Ada, 34392 Montpellier Cedex 5, FRANCE
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

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Abstract

e Abstract: In this paper, we present a method for analyzing the testability of a circuit during high level synthesis. The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of description of a circuit is (from the behavioral level-initial specification-down to the Register Transfer Level-high level synthesis output-). Experiments show the good correlation of the so-obtained testability measures with gate-level testability measures (e.g. Scoap). The proposed measures are used to guide high level synthesis towards the generation of easily SATPG testable datapaths.