A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Designing Circuits with Partial Scan
IEEE Design & Test
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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In this paper, we present a method for quickly identifying the scan path chain of datapaths. The originality of the method resides in working with both RT and gate-level level descriptions of circuits. The proposed technique results in a very significant reduction on the CPU time required for scan path selection. We investigate also some directions for the incorporation of partial scan methodology within High Level Synthesis for Testability.