REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
Scanning datapaths: a fast and effective partial scan selection technique
Proceedings of the conference on Design, automation and test in Europe
High-Level Test Synthesis of Digital VLSI Circuits
High-Level Test Synthesis of Digital VLSI Circuits
Introduction to Evolutionary Computing
Introduction to Evolutionary Computing
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Datapath synthesis using a problem-space genetic algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The main approach of this paper is utilizing bio-inspired evolutionary strategies for high level test synthesis. In this paper a genetic algorithm (GA) is implemented to schedule a data-flow graph considering latency. Also, module binding is performed with another GA concurrently, considering resource constraints. The register allocation is performed using another GA which minimizes the number of registers. Then a co-evolutionary strategy merges the results of these three solutions, targeting testability improvement. Experimental results show using the proposed approach results in improvement in fault coverage with no or negligible overhead in area and delay.