High-Level Test Synthesis of Digital VLSI Circuits

• Authors: Mike Tien-Chien Lee
• Venue: High-Level Test Synthesis of Digital VLSI Circuits
• Year: 1997

From the Publisher:Here is the first book to propose HTS as a complete, more effective design approach. The author explains how HTS, unlike most existing high-level synthesis techniques that optimize the circuit architecture for area and performance only, is able to explore the synthesis freedom provided at high level to derive an inherently testable architecture at low or even no overhead. By permitting testing from the earliest design stages to minimize or even eliminate serious testing problems, HTS boosts design quality and shortens the development cycle. The book provides an introduction to HTS and helps you develop a comprehensive understanding of this emerging technology by presenting: 聲 The background of HTS terminology, operation scheduling, and resource allocation algorithms used in high-level synthesis 聲 A discussion of various HTS techniques for both scan and built-in self-test methodologies 聲 Coverage of register-transfer level test synthesis 聲 A self-contained introduction to high-level synthesis algorithms and digital testing 聲 Examples of several effective HTS schemes for highly testable digital circuits, assuming non-scan or partial-scan test strategies 聲 A current survey of representative HTS systems For VLSI engineers and developers involved in design-for-test methodology and CAD tool development, this pioneering work provides a first look at the promising HTS technology. It also is a highly informative reference for industry and academic researchers and graduate students interested in this new area.