Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-Level Test Synthesis of Digital VLSI Circuits
High-Level Test Synthesis of Digital VLSI Circuits
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Estimation and Consideration of Interconnection Delays during High-Level Synthesis
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A BIST scheme for RTL circuits based on symbolic testability analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BIST hardware synthesis for RTL data paths based on test compatibility classes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.