A wiring-aware approach to minimizing built-in self-test overhead
Journal of Computer Science and Technology
| Hi-index | 0.00 |
In deep submicron designs the interconnection delays will have a strong in.uence on the timing behavior of the circuits. Traditional high-level synthesis systems, however, do not consider interconnection delays. In this paper we propose techniques that address this problem by estimating the delay and area cost of the interconnections during the high-level synthesis process. The interconnection delays are used to guide the scheduling, allocation, and binding, which are performed in a single step in our approach. The experimental results show the importance of taking the effects of the interconnections into account.