Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Concurrent error detection at architectural level
Proceedings of the 11th international symposium on System synthesis
On-line test for fault-secure fault identification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-Level Test Synthesis of Digital VLSI Circuits
High-Level Test Synthesis of Digital VLSI Circuits
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An efficient comparative concurrent Built-In Self-Test technique
ATS '95 Proceedings of the 4th Asian Test Symposium
Diversity techniques for concurrent error detection
Diversity techniques for concurrent error detection
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Journal of Electronic Testing: Theory and Applications
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems
ITC '04 Proceedings of the International Test Conference on International Test Conference
Concurrent test for digital linear systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel and efficient approach for reliability enhancement at the RT level. The reliability enhancement is performed by utilizing the available resources of a design in their dead intervals. Such resources are used for constructing dynamic TMR structures that can change per clock cycle. In this method all resources participate in constructing TMR structures at least once per a system input to output flow.To evaluate the proposed fault tolerance technique we consider dependability, and area/latency overhead imposed on a circuit by applying our method. In order to evaluate dependability, faults are injected into our test circuits before and after applying our algorithm and fault coverage is measured. Experimental results show that after applying our method, fault coverage is significantly reduced indicating that the reliability of designs is improved.