The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
CHEOPS: cost-driven heuristic for partial scan
Economics of design and test for electronic circuits and systems
A test methodology for finite state machines using partial scan design
Journal of Electronic Testing: Theory and Applications
Designing Circuits with Partial Scan
IEEE Design & Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan with pre-selected scan signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Layout driven selecting and chaining of partial scan flip-flops
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Layout Driven Selection and Chaining of Partial Scan Flip-Flops
Journal of Electronic Testing: Theory and Applications
Partial Scan with Preselected Scan Signals
IEEE Transactions on Computers
Scanning datapaths: a fast and effective partial scan selection technique
Proceedings of the conference on Design, automation and test in Europe
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
Partial Scan Testing on the Register-Transfer Level
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Partial Scan Using Multi-Hop State Reachability Analysis
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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