A Unified DFT Approach for BIST and External Test

Authors:
M.-L. Flottes;C. Landrault;A. Petitqueux
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, LIRMM/University of Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France. flottes@lirmm.fr;Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, LIRMM/University of Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France;Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, LIRMM/University of Montpellier 2, 161 rue Ada, 34392 Montpellier Cedex 5, France
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2003

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Abstract

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.