On Selecting Flip-Flops for Partial Reset

Partial scan selection for user-specified fault coverage

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits

IEEE Transactions on Computers

Low-cost sequential ATPG with clock-control DFT

Proceedings of the 39th annual Design Automation Conference

A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications

On Full Reset as a Design-For-Testability Technique

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Proceedings of the 41st annual Design Automation Conference

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan

IEEE Transactions on Computers