Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Designing Circuits with Partial Scan
IEEE Design & Test
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
On Combining Design for Testability Techniques
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Selecting Flip-Flops for Partial Reset
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Invalid State Identification for Sequential Circuit Test Generation
ATS '96 Proceedings of the 5th Asian Test Symposium
EDTC '95 Proceedings of the 1995 European conference on Design and Test
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
On the selection of a partial scan path with respect to target faults
EURO-DAC '91 Proceedings of the conference on European design automation
A complexity analysis of sequential ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified DFT Approach for BIST and External Test
Journal of Electronic Testing: Theory and Applications
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This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.