On Combining Design for Testability Techniques

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits

IEEE Transactions on Computers

A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications

Cost-Driven Ranking of Memory Elements for Partial Intrusion

IEEE Design & Test

15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

IEEE Transactions on Computers

On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Proceedings of the 41st annual Design Automation Conference

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design