Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
On Combining Design for Testability Techniques
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On Selecting Flip-Flops for Partial Reset
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
IEEE Transactions on Computers
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Design-for-testability (DFT ) for synchronous sequentialcircuits causes redundant faults in the original circuit to bedetectable in the circuit with DFT logic. It has beenargued that such faults should not be detected in order toavoid reducing the yield unnecessarily. One way to dealwith such faults is to mask (or ignore) their fault effectswhen they appear on the circuit outputs, without maskingthe detection of faults that need to be detected. To investigatethe extent to which this can be accomplished, wedescribe a procedure for masking the effects of redundantfaults of the original circuit under a given test set generatedfor the circuit with DFT logic. The procedureattempts to maximize the number of redundant faults thatare masked while minimizing (or holding to zero) thenumber of other masked faults.