A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Isomorph-Redundancy in Sequential Circuits
IEEE Transactions on Computers
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A genetic approach to test application time reduction for full scan and partial scan circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Scan Design Using Standard Flip-Flops
IEEE Design & Test
On the Properties of Irredundant Logic Networks
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Isomorph-Redundancy in Sequential Circuits
IEEE Transactions on Computers
Does retiming affect redundancy in sequential circuits?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or testability-targeted synthesis approaches. We show that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model. Every pair of states can easily be distinguished in the modified machine, thus making it easily testable. The augmented logic is also universal, i.e., independent of the state diagram or the circuit structure of the given machine. Analysis of benchmark circuits reveals that its hardware overhead is much less compared to that of full scan design.