Scan Design Using Standard Flip-Flops

Authors:
Sudhakar Reddy;R. Dandapani
Affiliations:
University of Iowa;University of Colorado
Venue:
IEEE Design & Test
Year:
1987

Citing 0
Cited 5

Testable design of non-scan sequential circuits using extra logic

ATS '95 Proceedings of the 4th Asian Test Symposium
A genetic approach to test application time reduction for full scan and partial scan circuits

VLSID '95 Proceedings of the 8th International Conference on VLSI Design
On Full Reset as a Design-For-Testability Technique

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
On RTL Scan Design

ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan

IEEE Transactions on Computers

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Abstract

Classical scan designs require properly augmented flip-flops, often called scan flip-flops. Problems stem from the high areaoverhead implied by the need for these flip-flops or the inability to modify standard flip-flops. The authors outline a methodto design easily testable sequential circuits that achieve scan designs using standard (unmodified) flip-flops.