An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Scan Design Using Standard Flip-Flops
IEEE Design & Test
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Dynamic test Sequence compaction for Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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Full scan and partial scan are effective design-for-testability techniques for achieving high fault coverage. However, test application time can be high if long scan chains are used. Reductions in test application time can be made if flip-flop values are not scanned in and out before and after every test vector is applied. Previous research has used deterministic fault-oriented combinational and sequential circuit test generators in generating test vectors and sequences and in deciding when to scan the flip-flops. In this work we use genetic algorithms to generate compact test sets which limit the scan operations. Results for the ISCAS89 sequential benchmark circuits show that significant reductions in test application time can be achieved, especially for partial scan circuits.