An algorithm to reduce test application time in full scan designs

Testability forecasting for sequential circuits

ATS '95 Proceedings of the 4th Asian Test Symposium

A genetic approach to test application time reduction for full scan and partial scan circuits

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

On Improving the Stuck-at Fault Coverage of Functional Test Sequences by Using Limited-Scan Operations

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A Case Study on t e Implementation of t e Illinois Scan Architecture

ITC '01 Proceedings of the 2001 IEEE International Test Conference

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests

IEEE Transactions on Computers

ATPG for heat dissipation minimization during test application

ITC'94 Proceedings of the 1994 international conference on Test

A test clock reduction method for scan-designed circuits

ITC'94 Proceedings of the 1994 international conference on Test

Reduced scan shift: a new testing method for sequential circuits

ITC'94 Proceedings of the 1994 international conference on Test

Autoscan: a scan design without external scan inputs or outputs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems