An algorithm to reduce test application time in full scan designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
IEEE Spectrum
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Design & Test
Reconfiguration techniques for a single scan chain
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan based test techniques offer a very efficientalternative to achieve high fault coverage when compared to functional pattern testing. As circuit sizesgrow ever larger, test data volume and test application time grow unwieldy even in the very efficient scanbased designs. The Illinois Scan Architecture is a lowcost alternative to conventional scan. In this paper,we present the first ever reported case study of theeffectiveness of the Illinois Scan Architecture on anindustrial circuit.