Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
| Hi-index | 0.04 |
A major drawback in using scan techniques is the long test application times incurred in shifting test data in and out of a device. This problem assumes even greater significance with the rapid growth in both the number of test patterns and scan registers occurring in complex VLSI designs. This paper presents a novel methodology based on reconfiguring a single scan chain to minimize the shifting time in applying test patterns to a device. The main idea is to employ multiplexers to bypass registers that are not frequently accessed in the test process and hence reduce the overall test application time, For partitioned scan designs, we describe two different modes of test application which can be used to efficiently tradeoff the logic and routing overheads of the reconfiguration strategy with the test application time. In each case we provide detailed analysis and optimization techniques to minimize the number of added multiplexers and the corresponding test time. Implementation results on two data path circuits demonstrate test time reductions as large as 75% over traditional schemes at the expense of 1-3 multiplexers