A test clock reduction method for scan-designed circuits

Authors:
Jau-Shien Chang;Chen-Shang Lin
Affiliations:
Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.;Department, of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 6
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Abstract

In this paper, a novel test clock reduction method is proposed to generate a compact test scheme for scan-designed sequential circuits. The method comprises of two phases. First, from a given compact combinational test set, sequential fault propagation is performed after each scan-in operation to propagate the activated faults and simultaneously detect other undetected faults as many as possible. In the second phase, two active overlapping techniques are developed to maximize the overlap between successive scan-in patterns in pure scan mode. The experimental results show that the number of test clocks are reduced to half of fullscan. Furthermore, in comparison with the mix-mode test generator, TARF[4] requires 54% more test clocks than ours.