An artificial intelligence approach to test generation
An artificial intelligence approach to test generation
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '79 Proceedings of the 16th Design Automation Conference
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A state traversal algorithm using a state covariance matrix
DAC '93 Proceedings of the 30th international Design Automation Conference
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
1988 Design Automation Conference: Guest Editorial
IEEE Design & Test
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
A parallel sequential test generation system DESCARTES based on real-valued logic simulation
ATS '95 Proceedings of the 4th Asian Test Symposium
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A practical approach to instruction-based test generation for functional modules of VLSI processors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
DNA and quantum based algorithms for VLSI circuits testing
Natural Computing: an international journal
An automatic test pattern generator for large sequential circuits based on genetic algorithms
ITC'94 Proceedings of the 1994 international conference on Test
A test clock reduction method for scan-designed circuits
ITC'94 Proceedings of the 1994 international conference on Test
Behavioral test generation using mixed integer non-linear programming
ITC'94 Proceedings of the 1994 international conference on Test
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 0.00 |
This paper describes the application of a concurrent fault simulator to automatic test vector generation. As faults are simulated in the fault simulator a cost function is simultaneously computed. A simple cost function is the distance (in terms of the number of gates and flip-flops) of a fault effect from a primary output. The input vector is then modified to reduce the cost function until a test is found. The paper presents experimental results showing the effectiveness of this method in generating tests for combinational and sequential circuits. By defining suitable cost functions, we have been able to generate: 1) initialization sequences, 2) tests for a group of faults, and 3) a test for a given fault. Even asynchronous sequential circuits can be handled by this approach.