Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
RTG: automatic register level test generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Experiments on the synthesis and testability of non-scan finite state machines
EURO-DAC '92 Proceedings of the conference on European design automation
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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The problem of test generation for non-scan sequential VLSI circuits is addressed. A novel method of test generation that efficiently generates test sequences for stuck-at faults in the logic circuit by exploiting register-transfer-level (RTL) design information is presented. Our approach is targeted at chips with data-path like STG.The problem of sequential test generation is decomposed into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. Standard combinational test generation algorithms are used to generate test vectors for stuck-at faults in the logic-level implementation. The required state corresponding to the test vector is justified using a fault-free justification step that is performed using the RTL specification. Similarly, if the effect of the fault has been propagated by the test vector to the flip-flop inputs alone, the faulty state produced is differentiated from the true next state by a differentiation step that uses the RTL specification.New and efficient algorithms for fault-free state justification and differentiation on RTL descriptions that contain arithmetic as well as random logic modules are described. Unlike previous approaches, this approach does not require the storage of covers or a partial STG and can be used to generate tests for entire chips without scan. Exploiting RTL information, together with a new conflict resolution technique results in improvements of up to 100X in performance over sequential test generation techniques restricted to operate at the logic level. We have successfully generated tests for the viterbi speech processor chip [18].