A parallel sequential test generation system DESCARTES based on real-valued logic simulation

Authors:
H. Date;M. Nakao;K. Hatayama
Affiliations:
-;-;-
Venue:
ATS '95 Proceedings of the 4th Asian Test Symposium
Year:
1995

Citing 6
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Abstract

This paper presents a parallel, automatic test generation system, DESCARTES, for synchronous sequential circuits. This system parallelizes the test generation algorithm based on real-valued logic simulation. By addition of a redundant fault identification program and an algorithmic test generation program, test generation is speeded up and test quality is improved. Experimental results for ISCAS '89 benchmark sequential circuits illustrate the efficiency of this approach.