An architectural level test generator based on nonlinear equation solving
Journal of Electronic Testing: Theory and Applications
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A Test-Pattern-Generation Algorithm for Sequential Circuits
IEEE Design & Test
Sequential Test Generation Based on Real-Value Logic
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Design for Testability A Survey
IEEE Transactions on Computers
Functional Testing of Microprocessors
IEEE Transactions on Computers
IEEE Design & Test
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
IEEE Transactions on Computers
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This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach.