Digital logic testing and simulation
Digital logic testing and simulation
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A new approach to program testing
Proceedings of the international conference on Reliable software
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Graph Theory With Applications
Graph Theory With Applications
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Methodology for the Generation of Program Test Data
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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This paper describes a novel technique to generate test vectors for single stuck-at faults using the behavioral description of the circuit function and the mapping from the behavior into the hardware that implements it. The test vector generation problem is formulated as a Mixed Integer Non-Linear Programming (MINLP) problem, and the test vectors are obtained by solving a series of MINLPs. The technique has been implemented and results from this approach show an order of magnitude speed up in test generation compared to existing gate-level sequential test generation tools.