Embedded System Design: A Unified Hardware/Software Introduction
Embedded System Design: A Unified Hardware/Software Introduction
A Binary Markov Process Model for Random Testing
IEEE Transactions on Software Engineering
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
On choosing test criteria for behavioral level hardware design verification
HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Achieving the Quality of Verification for Behavioral Models with Minimum Effort
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Confidence-Based Reliability And Statistical Coverage Estimation
ISSRE '97 Proceedings of the Eighth International Symposium on Software Reliability Engineering
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Behavioral test generation using mixed integer non-linear programming
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 0.00 |
This paper presents two additional strategies to reduce simulation time for Bayesian based stopping rules in VHDL model verification. The first is that a semi-random variable is defined and the data staying in the semi-random variable range are skipped when stopping rule is running, and a turning point that can partition a random variable into a semi-random and a genuine random variable is chosen. The second is that the old values of parameters are kept when phases of stopping rule change. 12 VHDL models are examined, and the simulation results demonstrate that more than approximately 25% of clock cycles are reduced when using the two proposed strategies with 0.6% branch coverage rate loss