Bottleneck removal algorithm for dynamic compaction and test cycles reduction

Authors:
Srimat T. Chakradhar;Anand Raghunathan
Affiliations:
C&C Research Laboratories, NEC USA, Princeton, NJ;Department of Electrical Engineering, Princeton University, Princeton, NJ
Venue:
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Year:
1995

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