Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Random limited-scan to improve random pattern testing of scan circuits
Proceedings of the 38th annual Design Automation Conference
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test sequence compaction by reduced scan shift and retiming
ATS '95 Proceedings of the 4th Asian Test Symposium
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for transition faults under transparent-scan
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
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