A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Overall consideration of scan design and test generation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Designing Circuits with Partial Scan
IEEE Design & Test
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A Test-Clock Reduction Method for Scan-Designed Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
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This paper presents a method to compact test sequences for full scan designed circuits by using the reduced scan shift and the retiming. The reduced scan shift, which we previously proposed, can compact test sequences by omitting unnecessary scan shifts. In this work, retiming, which repositions flip-flops, is introduced to enhance the effect of the reduced scan shift. When the number of flip-flops is reduced by the retiming, the test length is also reduced. Furthermore, this paper shows that the test length can be reduced even when the number of flip-flops is not reduced by the retiming. Under applying the reduced scan shift, the change of the control requirement to flip-flops by the retiming causes the reduction of scan shifts. Test vectors for the retimed circuit can be obtained by modifying the test vectors for the original circuit. Then the computing time to newly generate test vectors can be saved. Finally experimental results are given to show the effectiveness of the proposed method.