The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan with pre-selected scan signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Proceedings of the IEEE International Test Conference 2001
A genetic approach to test application time reduction for full scan and partial scan circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Reducing test application time in scan design schemes
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A novel scheme to reduce test application time in circuits with full scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudo-exhaustive built-in TPG for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A test application method to reduce the test application time in full scan designs is presented. It can be used either during or after the test pattern generation phase so that one or more patterns can be reached from an already scanned pattern using scan reapply or scan shift operations. The presented approach is based on established methods for reachability analysis in sequential verification and a fault grading algorithm to ensure that all targeted faults are covered.