Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Test compaction for transition faults under transparent-scan
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reducing the switching activity of test sequences under transparent-scan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Autoscan: a scan design without external scan inputs or outputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We describe a static compaction procedure for full-scan circuits. The procedure accepts a (compact) test set generated for the combinational logic of the circuit and produces a test set with reduced test application time and tester memory requirements. The reductions are achieved by combining pairs of tests. When a pair of tests is combined, the scan operation required between the two tests is replaced with a limited scan operation. Under a limited scan operation a scan chain of length L is shifted a number of positions S ≤ L. As a special case, S = 0 implies that the scan operation between two tests is eliminated altogether. We introduce several techniques to ensure that consideration of test pairs can be done efficiently and results in very high levels of test compaction for benchmark circuits.