HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
ATS '99 Proceedings of the 8th Asian Test Symposium
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design space exploration for aggressive test cost reduction in CircularScan architectures
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in constructing the subsequent test vector. An algorithm is provided for stitching test vectors that retains full fault coverage while appreciably reducing time and tester requirements. The analysis provided enables significant compression ratios, while necessitating no hardware outlay whatsoever, making the technique we propose particularly suitable for SOC testing. The test time benefits necessitate no MISR utilization, ensuring no consequent aliasing loss. We examine a number of implementation considerations for the new compression technique and we provide experimental data that can be used to guide an eventual commercial implementation. Experimental data confirms the significant test application time and tester memory reductions.