HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Fault Dictionary Size Reduction through Test Response Superposition
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
IEEE Transactions on Computers
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Virtual Compression through Test Vector Stitching for Scan Based Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Cost Reduction Through A Reconfigurable Scan Architecture
ITC '04 Proceedings of the International Test Conference on International Test Conference
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan-based designs effectively reduce test generation complexity and thus deliver improved fault coverage. Nevertheless, the traditional scan architectures suffer from increased test time and test data volume. The CircularScan architecture (Arslan and Orailoglu) provides a flexible environment for test cost reduction. The new scan design enables the use of the captured response of the previously applied test pattern as a template. The subsequent pattern is loaded by efficiently performing the necessary changes on the template through the functionality provided by the new architecture, conceptually exploiting the inherent low specified bit density of the test patterns. We explore the space of possible design alternatives built on the CircularScan architecture; the design alternatives are presented with accompanying test application methods. The experimental results indicate a substantial test cost reduction, reaching 90% levels. The proposed scheme is not only easily scalable but also promises further reductions in test cost when applied to large state of the art ICs.