Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
A contraction algorithm for finding small cycle cutsets
Journal of Algorithms
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Introduction to algorithms
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Decomposable searching problems and circuit optimization by retiming: two studies in general transformations of computational structures
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
Hi-index | 14.98 |
A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose two techniques (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming. For non-timing-driven partial scan, we employ retiming to rearrange the flip-flops of the circuit, so that its functionality is preserved, while the number of flip-flops that are needed to break all cycles and bound the sequential depth is significantly reduced. For timing-driven partial scan, we propose a retiming-based technique that reduces the overall area overhead required to achieve the clock period bound. Experimental results on the ISCAS'89 circuits show the benefit of our approach in both timing-driven and non-timing-driven partial scan