Non-scan design-for-testability techniques for sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Fast Sequential ATPG Based on Implicit State Enumeration
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Warning: 100% Fault Coverage May Be Misleading!!
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
On Selecting Flip-Flops for Partial Reset
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Full-Symbolic ATPG for Large Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Scan Design Using Standard Flip-Flops
IEEE Design & Test
Built-in generation of weighted test sequences for synchronous sequential circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Improving the proportion of at-speed tests in scan BIST
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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Full scan design allows every combinationally irredundant fault in a synchronous sequential circuit to be tested. In this paper, we derive a similar result applicable to design-for-testability techniques that use reset instead of scan. We show that if reset states can be selected arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault which is not sequentially or combinationally redundant. Thus, increasing the circuit controllability is sufficient for detecting every irredundant fault, and improving its observability is not necessary for this purpose. We also show that of all the states of the circuit, it is sufficient to consider as possible reset states only the states extracted from a complete combinational test set. We describe two procedures to select the reset states and perform test generation for a given synchronous sequential circuit. Experimental results are given for ISCAS-89 benchmark circuits.