Built-in generation of weighted test sequences for synchronous sequential circuits

  • Authors:
  • Irith Pomeranz;Sudhakar M. Reddy

  • Affiliations:
  • Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA;Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

  • Venue:
  • DATE '00 Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2000

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Abstract